Advances in semiconductor manufacturing technology during the last decade have enabled integration of wireless transceiver systems into a single chip and provided low cost, system-level solutions. As the manufacturing cost has been reduced, production test cost has become an increasingly larger portion of the total manufacturing cost. In conventional test approaches, the specifications of the radio frequency (RF) system under test are measured and compared to predefined test bounds to determine pass/fail for the system. Each specification measurement involves stimulating the DUT with a different test stimulus under a different test circuit configuration. In addition, due to the high operating frequency involved, production test of RF circuits requires the use of expensive measurement systems and elaborate measurement setups. These issues associated with RF circuit production test increase RF test cost and thereby increase the overall manufacturing cost of high frequency RF devices.
Another problem area for a wireless system under test is diagnosis of component circuits making up the system since the ability to do failure diagnosis is important for design debugging and rapid yield ramp-up with new silicon technologies. However, in a highly integrated RF transceiver with multiple sub-modules, failure diagnosis is difficult due to the infeasibility of probing internal RF nodes.
Some methods of RF testing using embedded test sensors have been tried in the past. In one case, the method required long test time and had difficulty handling multiple parametric faults. In other cases, the methods did not take into account the effect of internal stimulus changes by the performance metrics of submodules. Further, the tests required multiple embedded test sensors to extract various specification features, and therefore, the sensors used too much die area and were susceptible to failure. Such failures degrade the manufacturing yield.